Sean Lie
@seanlie • 15,866 subscribers
CTO @Cerebras
Videos
I joined AMD right after graduating from MIT. Two stints there and a decade building Cerebras later, I still lose sleep over how much memory and compute to put on a chip. I’ve spent my entire career in computer architecture, and I’ve never seen the problems change this quickly. Models keep getting larger. The demands on the hardware keep growing. Decisions about where to put memory and how to connect it have become central to what people can build with AI. We chose SRAM for its bandwidth. Now we’re working on wafer-scale stacked DRAM to give larger models more capacity while preserving fast inference. That brings us back to some very physical problems: how to power it, cool it, and manufacture it reliably. This is the work I love. In part two of our AMA, I answered your questions about those decisions and where we’re going next. 0:30 What changes between CS4, CS5, and CS6? 2:19 HBM already stacks memory. What’s different here? 3:34 We chose SRAM for speed. Why add DRAM? 4:52 Drawing the stack is easy. Making it work isn’t. 7:23 The memory-versus-compute decision that keeps me up at night
Sean Lie30,739 次观看 • 15 天前
When we started Cerebras, we knew we would have to solve difficult problems in yield, power, and cooling. What became clear was that making wafer-scale work would require rethinking almost the entire system. Today, we answered questions from the community about those engineering decisions, how we run larger models, and what it takes to program the hardware. 2:15 Why hasn't NVIDIA gone wafer-scale? 4:10 How we build a working chip out of an imperfect wafer 8:07 What happens when a model won't fit on one wafer? 11:34 Why we chose SRAM over HBM 14:26 How much of a barrier is NVIDIA's CUDA moat?
Sean Lie32,611 次观看 • 1 个月前
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