animated DDR fanout algorithm

what is up with the confetti?

That is the tail of the state space being explored, each of the points represents a trace that has yet to be explored, about 20k traces are explored per second

can't help but notice it is exploring the space under the BGA, without the bga being fanned out. space available will be different when vias are present, and it is fair to assume most pins will require a via. might I suggest that BGA routing should evaluate space after all the vias for the bga have been placed already

i was surprised to see that the ground/vcc vias weren't placed BEFORE routing buses I don't have a good answer to this at the moment, we have to run experiments. To me, this algorithm looks very naive still! It should do wall-following and other tricks to run faster

watching the video, it is clear that a fanout phase does exist, but it didn't fan out the vias until after a bunch of traces were already routed.

the algorithm process with ai is often just suggesting things like this then (after 2 hours of implementation) watching the animation to see 1) if it did it right 2) if it worked 😁

hella sick. what do you call this?

Hah the tscircuit fanout solver, no extra ceremony 😁

Bro…….. Go to sleep. You're making us look bad out here. Personally I'd call it the ripple route.

Can’t sleep! BGA fanouts keeping me up at night 😱

is this tscircuit-autorouter?

fanout-solver!

satisfying to watch. isn’t this basically the TSP ( travelling salesman problem?

Super cool

Cool! :D

waves 🌊

It's just a reaction-diffusion PDE

Why is the ddr on the right where the ddr pins are on the left side of the IC ? You are running under the soc and you’ll have difficulties to fan out other signals/power