How we deploy multi-trillion parameter models at scale Today, let's break down the math for how Cerebras: 1. Fits the full model into on-chip memory 2. Maps the model across multiple chips 3. Handles a high # of concurrent requests

@cerebras @MilksandMatcha How many wafers are needed to run astra 6.1?

ARE YOU KIDDING ME. **ONLY** 59 Wafers? Help us understand the economics behind the COST =When each Nvidia's HBM 13Terrabyte equivalent at the the fraction of the power draw , 26 Terrabyte if we include cpu memory!! 20 CS4 servers (59 wafers) would cost about 100+ Million dollars appx on precendent cost!! vs the same HBM capacity in fast memory would be 3.5 mil??

@cerebras @MilksandMatcha The model was also quantized down condensed, less accurate but for faster inference processing from F16 to F4. Precisely because if their SRAM cap, power draw, cost of compute.

@cerebras @MilksandMatcha very good format to teach frontier scale production systems

@cerebras @MilksandMatcha Awesome.... We can leverage this to deploy large sequence model or large transactions model as we;;

@cerebras @MilksandMatcha On-chip KV still caps concurrent decode

@cerebras @MilksandMatcha Epic @seanlie

@cerebras @MilksandMatcha how does prefill happen ? that happens on a CPU outside the wafer scale engine and then tokens are pushed to Wafers #1 layer ?

@cerebras @MilksandMatcha fuck your mother. die with your ugly company cerebullshit

@cerebras @MilksandMatcha Love Cerebras

@cerebras @MilksandMatcha What's the bandwidth on your RDMA? Wouldn't that become a bottleneck?

Sean Lie, Cerebras CTO, walked through a whiteboard demo showing how they run a 3-trillion-parameter model called Kimi K3. The math is clean: each giant wafer has 44 GB of fast on-chip memory. They slice the model into layers, put one or two layers per wafer, and end up needing 59 wafers. • That’s about 20 full CS-4 systems. Here is the part that matters for an investor. Each CS-4 rack is estimated at $5.5–8 million. Twenty of them is $110–160 million in capital just to hold one model. Those 20 racks give you a total of only about 2.6 TB of fast on-chip memory across the whole cluster. An NVIDIA GB200 NVL72 rack costs roughly $3 million and packs more than 13 TB of fast HBM memory into a single system. One NVL72 can keep the model resident without slicing it across dozens of machines. •Power draw per rack is comparable (Cerebras around 125–135 kW, NVL72 around 120–140 kW). The difference is utilization. Independent measurements cited by Culper Research show Cerebras systems can sit at 70–80% of peak power even when idle. The reason is practical: a chip the size of a dinner plate expands and contracts with temperature. To keep it from cracking, the company appears to run continuous “dummy” operations so the wafer never fully cools. NVIDIA GPUs drop to roughly 20% when idle. In an era of high electricity prices, that gap compounds every hour the machines are not fully busy. Culper also argues the wafers may only last 1.5–2.5 years in real use, shorter than the 3–5 year life Cerebras used in its S-1. If true, the already high purchase price has to be amortized faster, and large multi-year deals look less attractive. Cerebras has shown it can map a big model across many wafers. What it has not shown is that this is cheaper, more energy-efficient, or more reliable than simply buying NVIDIA systems that hold the same model in far more fast memory at a fraction of the capital cost. For most investors, the whiteboard is interesting. The balance sheet comparison is decisive. Here are the primary sources that back the claims in the posts: 59 wafers for Kimi K3 (Cerebras’s own demo) •Video / whiteboard walkthrough: •Companion write-up: •Same numbers on X: CS-4 power (125–135 kW range) •SemiAnalysis: (explicitly states 125–135 kW TDP) •The Register: (120–140 kW estimate) •ServeTheHome / other coverage confirming the same range from the power-doubling design. CS-4 memory (44 GB SRAM per wafer, 132 GB per rack) •Cerebras CS-4 page / specs: and • / ServeTheHome datasheets list 3 × 44 GB = 132 GB SRAM, no HBM. NVIDIA GB200 NVL72 pricing (~$2.8–3.5M) and memory (~13.4 TB HBM3e) •Gatewell / OEM quotes: ($2.8–3.6M range) •QuantaCloud / multiple reports: (≈$3M, HSBC/Wolfe/Tom’s Hardware estimates) •Spheron / others: (13.4 TB HBM3e, ~120 kW) •AXION listing example: (~$2.49M listed, 13.5 TB) Culper Research claims (idle power, dummy tokens, lifespan) •Full report PDF: •Original X thread: •Coverage of the ISPASS / Harvard-Meta idle-power measurement and dummy-token claims: •Useful-life change (1.5–3 yrs → 3–5 yrs) is documented in Cerebras’s own draft filings vs April 2026 S-1 (cited in the Culper report and subsequent coverage). Notes on pricing
Cerebras does not publish official CS-4 list prices. The $5.5–8M per rack figures used in the posts are estimates derived from prior-generation pricing and the fact that SemiAnalysis and others treat CS-4 as roughly similar cost to CS-3 while noting multi-system CapEx for frontier models quickly exceeds $20M. NVIDIA NVL72 pricing is better documented across multiple OEM in the $2.8–3.5M band.

This is the full transcript of Sean and Sarah's presentation. Feel free to run it through your favorite LLM to cross check references and data points = This was done by Grok, native llm to this platform = Sean: This is, again only possible because of the amount of SRAM that we have through wafer-scale integration on our wafer-scale engine. Let’s see if I can draw the logo from memory. Sarah: All right. Hi, Far. We are here today in Cerebras HQ in our hardware labs to answer one of the most frequently asked questions by you guys which is how do we at Cerebras support really large models? My name is Sarah. I lead developer experience and I am joined with… Sean: Hi, I’m Sean. I’m co-founder and CTO here at Cerebras. Sarah: So today we’re going to be walking through how we support Kimi K3, an open-source 3 trillion parameter model on our hardware. So a lot of people think that because our hardware is an SRAM-based design that it’s very hard to support very large models. And on traditional chips that are smaller that use SRAM that is in fact true. But because we have so much SRAM on our wafer-scale chip it actually maps really naturally and we can support even the largest models today. And we’re going to demonstrate that with a frontier-level model Kimi K3, which has 3 trillion parameters.Sean, can you walk us through some of the numbers that we’re starting with? Sean: Yeah absolutely. Kimi K3 has a total of 69 linear layers and 24 dense layers for a total of 93 total layers. And for this exercise we’re going to use a long context length of 256K. And here we’re going to assume the weights are quantized to 4 bits and we’re using 8-bit KV cache. So also this discussion includes examples and estimates for illustrative purposes. What that means is that actual wafer production configurations may vary and be slightly different from what you see here today. Sarah: But Sean, to jump straight in, you mentioned here we have 93 layers. Can you walk me through kind of what that looks like for this model specifically? Sean: Yeah, absolutely. So the structure of Kimi K3 is actually pretty simple. The 93 layers of Kimi K3 are actually broken up into groups of four layers each and each group has three linear layers and one dense layer. And this structure is repeated 23 times with one final dense layer at the end making up the total 93 layers. And each of these linear layers is using a special format attention that doesn’t require a KV cache. And so we can assume there’s no KV cache in the linear layer. But the dense layer is using a global dense attention that has all of the KV cache. So to start let’s understand our memory requirements and how much memory each layer of this model takes. Sarah: So Sean, can you walk us through here knowing that we have 44 gigabytes of on-chip memory per wafer what does it look like for each layer? Sean: Yeah, this is just simple arithmetic. If you take the Kimi K3 model it has a total of 3 trillion parameters. And if we’re storing every one of the parameters in four bits and there’s eight bits per byte this is a total of 1.5 terabytes of memory. We take that 1.5 terabytes and we divide it by the total of 93 layers and what we see is we have just a total of 16 gigabytes per layer. So we know that every layer in this model takes 16 gigabytes of memory. Sarah: We have here, can you walk me through like what this looks like in terms of linear layers and dense layers? Sean: Yeah absolutely. As I mentioned earlier the linear layers don’t have traditional KV cache and so we can ignore any additional state for this exercise and all of the KV cache is in the dense layers. And so that what that means is with 16 gigabytes per layer and 44 gigabytes total we can fit two linear layers on every wafer. One layer, two layers. The black is the wafer. And on the dense layers we will fit one layer on the wafer. (cont)below $CBRS $SPY $QQQ $NVDA $IWM

@cerebras @MilksandMatcha can I have a firmware job at cerebras? please?

@cerebras @MilksandMatcha Still down 64%

@cerebras @MilksandMatcha always love whitepapers that break down the memory bandwidth math instead of handwaving with peak TFLOPS

@cerebras @MilksandMatcha Any update on using photonics ? How is Renovus assisting with it?