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in-progress feature for showing return currents for DDR traces in tscircuit This video shows a ground pour void near the processor's dogboning which causes the return current to take a long path (this is bad!)

26,849 Aufrufe • vor 21 Tagen •via X (Twitter)

33 Kommentare

Profilbild von Lukas Henkel
Lukas Henkelvor 21 Tagen

Nice work! Still building on palace? Note though that signal pins don't have a single dedicated return path pad. The return current will flow through the closest/lowest impedance power pin in the vicinity. Same is true if you are using a power plane as return current reference only that the closest/lowest impedance stitching or decoupling capacitor will carry the return current.

Profilbild von Seve
Sevevor 21 Tagen

Yes we are doing a LOT with palace, and many of the results I have shown are from palace. I appreciate that, we are making a lot of progress thanks to that suggestion

Profilbild von Stocko 🦾
Stocko 🦾vor 21 Tagen

this should be a hyperparam in the autorouter

Profilbild von Seve
Sevevor 21 Tagen

Yep!!!!

Profilbild von Zack's Lab
Zack's Labvor 21 Tagen

nice!

Profilbild von Lukas Henkel
Lukas Henkelvor 21 Tagen

What's the frequency and color mapping btw? The current looks very spread out, looks like a lower bandwidth signal?

Profilbild von Seve
Sevevor 21 Tagen

A bit ashamed to say that this is very imprecise model/heuristic, I'm doing a balancing act right now to try to get the visualizer working prior to validating the results

Profilbild von fish
fishvor 21 Tagen

factorio pollution

Profilbild von Cornelius Robinson
Cornelius Robinsonvor 21 Tagen

That’s a really cool visualization.

Profilbild von RobitOverlord
RobitOverlordvor 21 Tagen

I cannot wait for Steve to have this. So useful

Profilbild von Edmund Humenberger
Edmund Humenbergervor 21 Tagen

It's not currents. It is fields.

Profilbild von Mattia
Mattiavor 21 Tagen

Now this looks helpful!

Profilbild von Georgios Konstantopoulos
Georgios Konstantopoulosvor 21 Tagen

wish i had this in university

Profilbild von FPGA Bandera
FPGA Banderavor 20 Tagen

my dude is playing factorio with a whole company

Profilbild von Peter Kuhar
Peter Kuharvor 21 Tagen

ok, this is super cool

Profilbild von Jambon radio ~The ramblings of a crazy man~
Jambon radio ~The ramblings of a crazy man~vor 21 Tagen

Does it dogbone bc it’s like a meniscus ?

Profilbild von Thusatharan
Thusatharanvor 21 Tagen

flagging that void before fab saves a whole respin tbh

Profilbild von Nathaniel Fargo
Nathaniel Fargovor 21 Tagen

I love how quickly you're iterating in general, and also on community feedback. What are the blockers for current analysis of all kinds, i.e. DC drop, power distribution. It would be awesome to design complex BGA PDNs using tools like this.

Profilbild von تعرف ايه عن المنطق؟
تعرف ايه عن المنطق؟vor 21 Tagen

This is bad stackup design. It does not need simulation.

Profilbild von Seve
Sevevor 21 Tagen

simulation confirms that it is a bad stackup, sometimes a first principles analysis is useful because now the AI can know the principle and not need to remember the heuristics

Profilbild von Andy Carson 
Andy Carson vor 20 Tagen

Does this only work for DDR traces? This looks so cool I wanna use it for slow stuff like SPI and I2C (don’t judge me).

Profilbild von Seve
Sevevor 20 Tagen

You could use it for anything, but it wouldn’t look as interesting because the signal path wouldn’t influence the return current as strongly

Profilbild von Matthew Campbell
Matthew Campbellvor 21 Tagen

Absolutely wild dude

Profilbild von Clem
Clemvor 21 Tagen

super cool :)

Profilbild von Qubitium
Qubitiumvor 21 Tagen

So cool.

Profilbild von 80% of X is BOT
80% of X is BOTvor 21 Tagen

What tool is this?

Profilbild von Dmytro Shevchenko 🇺🇦
Dmytro Shevchenko 🇺🇦vor 21 Tagen

looks like auto-tests for pcb 😅

Profilbild von ❤️
❤️vor 21 Tagen

Really cool

Profilbild von mr.y.singapore
mr.y.singaporevor 21 Tagen

very good and beautiful !

Profilbild von Petr Polášek
Petr Polášekvor 21 Tagen

So... it assumes that no current flows through dielectric or other nets than GND?

Profilbild von Steven Cheng
Steven Chengvor 21 Tagen

dogboning voids are a classic pain

Profilbild von alex_s168
alex_s168vor 21 Tagen

"this is bad", sure, but it might still work

Profilbild von Jan
Janvor 21 Tagen

That's nice. Can you generate TDR plot?

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