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Intel Foundry’s packaging technology continues to progress, with EMIB-T serving as the newest advancement this year. EMIB-T adds routing channels directly through tiny silicon bridges that connect different chips. By creating a more direct path for both energy and data, EMIB-T increases the efficiency and speed needed to power... show more

Intel

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36,865 Aufrufe • vor 4 Monaten •via X (Twitter)

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Profilbild von 陌冰🌍心软的人

陌冰🌍心软的人vor 4 Monaten

Yes

Profilbild von ⚜️ＣＨＯＬＥＶＡ

⚜️ＣＨＯＬＥＶＡvor 4 Monaten

@imnotharsh $INTC STRONG BUY LONG $5T ⚠️⚠️⚠️

Profilbild von Beat Eggli

Beat Egglivor 4 Monaten

The new projects connect your planning directly to the work your teams. Are doing and flexibly adapt to whatever your team needs at any point. Built like a spreadsheet, project tables give you a life canvas to filter, sort, and group issues and pull requests.

Profilbild von KiiChain

KiiChainvor 4 Monaten

EMIB-T pushing routing directly through silicon bridges shows how the industry is optimizing for faster data movement and lower power overhead. That’s critical for scaling large AI workloads.

Profilbild von satyam

satyamvor 4 Monaten

Cool

Profilbild von h

hvor 4 Monaten

@grok cool Je suis team intel depuis que mon premier pc était eeepc de asus avec le celron et donc j'ai la croissance et la qualité et la robustesse de INTEL !

Profilbild von C. Michael Randazzo

C. Michael Randazzovor 4 Monaten

When Zen premiered they called chiplets, "gluing together a processor" then hired the guy at AMD responsible for chiplets.

Profilbild von MVP

MVPvor 4 Monaten

Intel change the world

Profilbild von Margo

Margovor 4 Monaten

Market Chatter: What is this? why are you going to India instead of the US with these 1,800 jobs? 09:30 AM EDT, 05/29/2026 (MT Newswires) -- Intel (INTC) and 3DGS will invest about $3.3 billion to establish a semiconductor substrate manufacturing facility in India.

Profilbild von RTS Mobile

RTS Mobilevor 4 Monaten

This tech gets me excited, along with concepts like Cerebras wafer scale. Hope to see some Intel & Cerebras collaboration in the future, 2 disruptors taking down the mammoths.

Profilbild von MVP

MVPvor 4 Monaten

I love Intel. Love INTC

Profilbild von Felix Manufaktur

Felix Manufakturvor 4 Monaten

Silicon bridges with direct routing. This is exactly the packaging breakthrough we need for AI hardware to scale. I believe we are seeing a new era of chip manufacturing begin 🚀

Profilbild von Intel

Intelvor 4 Monaten

We love this attitude and see EMIB-T as a core part of how Intel is delivering the bandwidth and efficiency next‑gen AI workloads demand.

Profilbild von Felix Manufaktur

Felix Manufakturvor 4 Monaten

We stand at the beginning of a new era for high-performance silicon. EMIB-T proves advanced packaging is now the decisive factor for AI performance. 🚀

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New episode: Advanced packaging for AI chips, from wire bonds to TSMC CoWOS and Intel EMIB. Packaging is no longer an afterthought. It is the chip, and Intel's EMIB challenges TSMC's CoWOS. - Three CoWOS flavors: silicon, organic RDL, local bridges - EMIB embeds tiny bridges into the substrate, no interposer - EMIB-T and EMIB-M add through-silicon vias and power capacitors - Google is booking 3M TPUs on EMIB via MediaTek by 2028 - Package sizes keep climbing: 5.5x reticle today, 40x ahead Chapters: (0:00) "There Is No Chip Without the Packaging" (0:28) Intro and SpaceX IPO Day (5:15) What We're Covering: CoWOS, EMIB, Google (7:40) Simple Packaging: Wire Bonds to Flip Chip (17:07) What Makes Packaging "Advanced" (33:44) CoWOS: Three Flavors Explained (45:30) EMIB: Intel's Embedded Bridge Approach (52:47) EMIB-T and EMIB-M (57:31) CoWOS vs. EMIB Trade-offs (1:02:18) Google's 3M TPU EMIB Order Austin Lyons Vikram Sekar

New episode: Advanced packaging for AI chips, from wire bonds to TSMC CoWOS and Intel EMIB. Packaging is no longer an afterthought. It is the chip, and Intel's EMIB challenges TSMC's CoWOS. - Three CoWOS flavors: silicon, organic RDL, local bridges - EMIB embeds tiny bridges into the substrate, no interposer - EMIB-T and EMIB-M add through-silicon vias and power capacitors - Google is booking 3M TPUs on EMIB via MediaTek by 2028 - Package sizes keep climbing: 5.5x reticle today, 40x ahead Chapters: (0:00) "There Is No Chip Without the Packaging" (0:28) Intro and SpaceX IPO Day (5:15) What We're Covering: CoWOS, EMIB, Google (7:40) Simple Packaging: Wire Bonds to Flip Chip (17:07) What Makes Packaging "Advanced" (33:44) CoWOS: Three Flavors Explained (45:30) EMIB: Intel's Embedded Bridge Approach (52:47) EMIB-T and EMIB-M (57:31) CoWOS vs. EMIB Trade-offs (1:02:18) Google's 3M TPU EMIB Order Austin Lyons Vikram Sekar

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$INTC will be a major beneficiary of agentic AI as server CPU demand rises, GPU-to-CPU attach rates move closer to 1:1 and Intel can ramp supply through its internal foundry. Intel also has a second leg through advanced packaging with EMIB positioned as a CoWoS alternative that could reach ~$10B by 2030.

$INTC will be a major beneficiary of agentic AI as server CPU demand rises, GPU-to-CPU attach rates move closer to 1:1 and Intel can ramp supply through its internal foundry. Intel also has a second leg through advanced packaging with EMIB positioned as a CoWoS alternative that could reach ~$10B by 2030.

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What's the next step change in chip packaging technology? bubble boi: "The main difference between EMIB and CoWoS is CoWoS relies on what we call silicon interposers. They're like these huge plates where you put the chips on, and you start etching channels in between through the interposers." "An effect of that is that heat dumps into the interposers, just like anyone knows when they heat up popcorn, things expand and contract, and this creates worse yield." "NVIDIA's already seen this. Part of the reason why Blackwell had trouble ramping was all thermals, the package warping. That's a huge issue." "I think even TSMC knows it's a huge issue because in their further along roadmap, they don't really plan on adopting that for much longer. They're now going to a more Intel style thing where you use little bridges... smaller pieces of silicon to connect just the relevant parts." "What that effectively does is cut your costs 'cause you're using way less silicon, the thermals, the communication, it's centralized in one area."

What's the next step change in chip packaging technology? bubble boi: "The main difference between EMIB and CoWoS is CoWoS relies on what we call silicon interposers. They're like these huge plates where you put the chips on, and you start etching channels in between through the interposers." "An effect of that is that heat dumps into the interposers, just like anyone knows when they heat up popcorn, things expand and contract, and this creates worse yield." "NVIDIA's already seen this. Part of the reason why Blackwell had trouble ramping was all thermals, the package warping. That's a huge issue." "I think even TSMC knows it's a huge issue because in their further along roadmap, they don't really plan on adopting that for much longer. They're now going to a more Intel style thing where you use little bridges... smaller pieces of silicon to connect just the relevant parts." "What that effectively does is cut your costs 'cause you're using way less silicon, the thermals, the communication, it's centralized in one area."

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