On many high-speed designs it is necessary to have a ground-plane void underneath large pads to minimize the local impedance dip. I´ve used GPT-6 to create a script that reads the layerstack information through the Altium PCB API, isolate the target net- and pad class, creates an openEMS simulation,... run the simulation to find the pad void size that does not create an impedance dip compared to the trace that is attached to the pad and ultimately apply the calculated GND void expansion value to all pads in a user-defined net class. Currently all pads still receive the same expansion value. I will port the setup to use palace EM in order to automatically solve the expansion values for all different pad sizes/shapes in parallel which should be much faster than openEMS.show more

Altium looks really nice to use. Maybe one day I’ll get to try it

I like it :) I just wish they would take KiCAD as an example and increase the new features output. And fix long standing bugs...

I would imagine stability is extremely important, especially for large companies that use it. New features would therefore be quite slow

可以分享下脚本吗，想学习下思路

you should really make something from all these workflows you developed over the years. they are unique and would be very useful. "Lukas Toolbox for Altium" or something...

Quite useful for scripting the process.

What is the bandwidth?

It would be interesting to know your entire pipeline

Uh, that is pretty trick.

🔥

FINALLY we’re done with gpt6 pcb slop, now THIS is very fucking cool

one thing to watch when you parallelise. the target comes from whatever trace is attached, not the pad, so the same pad on two different traces wants two different voids. the sweep is pad shape times trace, not pad shape on its own

That is true but would be handled through the user defined input net classes which are usually impedance grouped

fair, net class covers it as long as the width is constant along the net. the one that bites is necking down for a bga escape, same net, two widths, and the pad sees the narrow one. probably a small enough set to special case

I´m not taking the geometry 1:1 from the design. I´m reconstructing it programmatically to in order to be able to make the FDTD mesh as small as possible. The script is only searching for trace segments so neck-down regions or polygons are not taken into account

@MrChallinger could this be of interest to you? (I'm not very technical, so it goes over my head!)

Solid workflow, but are you sure about the openEMS baseline? A wrong port setup shifts the impedance reference, and it seems to me you'd be tuning the void size against a wrong number.

It runs a transient TDR in openEMS and looks at the trace impedance 5mm in front of the pad. The open end is terminated into a PML boundary so I don´t see any reflections from this side. Therefore I would´t expect an influence from the port impedance as long as it´s a known value (which it is)

How high-speed does it need to be to require this? I don‘t think I have ever seen this in ~10Gbit/s lanes. Or could it be that it is more required in certain less-common stackups?

How can use altium like this ? Can u help me

the missing piece is attaching the solver inputs and version to each applied void. when the stackup changes, the agent should know which geometry is stale instead of silently preserving yesterday’s optimum.