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Playing around with ASIC render concepts. Need to work on visually differentiating the "active" module a bit more, but I think the bones are here.

56,281 Aufrufe • vor 2 Monaten •via X (Twitter)

7 Kommentare

Profilbild von Matthew Venn
Matthew Vennvor 2 Monaten

Have you seen ? For example this works great:

Profilbild von Ben Conrad
Ben Conradvor 2 Monaten

The grid. A digital frontier...

Profilbild von NanoPirate
NanoPiratevor 2 Monaten

Beautiful 🙌

Profilbild von LїckLїck🐈fellacat
LїckLїck🐈fellacatvor 2 Monaten

that's pretty neat!

Profilbild von 0xkato
0xkatovor 2 Monaten

In the X video, the active module reads clearly over green substrate, but loses separation in the angles where its pale interconnect texture crosses dense white routing below

Profilbild von BreakingTaps
BreakingTapsvor 2 Monaten

Agreed! Trying variations to lift / explode the active module more, and make the background less busy (darker colors, transparency, etc). Cheers!

Profilbild von FPGA Bandera
FPGA Banderavor 2 Monaten

Cant you use some kind of variation of map graphs?

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