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Playing around with ASIC render concepts. Need to work on visually differentiating the "active" module a bit more, but I think the bones are here.

56,199 views • 1 month ago •via X (Twitter)

7 Comments

Matthew Venn's profile picture
Matthew Venn1 month ago

Have you seen ? For example this works great:

Ben Conrad's profile picture
Ben Conrad1 month ago

The grid. A digital frontier...

NanoPirate's profile picture
NanoPirate1 month ago

Beautiful 🙌

LїckLїck🐈fellacat's profile picture
LїckLїck🐈fellacat1 month ago

that's pretty neat!

0xkato's profile picture
0xkato1 month ago

In the X video, the active module reads clearly over green substrate, but loses separation in the angles where its pale interconnect texture crosses dense white routing below

BreakingTaps's profile picture
BreakingTaps1 month ago

Agreed! Trying variations to lift / explode the active module more, and make the background less busy (darker colors, transparency, etc). Cheers!

FPGA Bandera's profile picture
FPGA Bandera1 month ago

Cant you use some kind of variation of map graphs?

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