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Playing around with ASIC render concepts. Need to work on visually differentiating the "active" module a bit more, but I think the bones are here.
56,199 просмотров • 1 месяц назад •via X (Twitter)
Комментарии: 7

Matthew Venn1 месяц назад
Have you seen ? For example this works great:

Ben Conrad1 месяц назад
The grid. A digital frontier...

NanoPirate1 месяц назад
Beautiful 🙌

LїckLїck🐈fellacat1 месяц назад
that's pretty neat!

0xkato1 месяц назад
In the X video, the active module reads clearly over green substrate, but loses separation in the angles where its pale interconnect texture crosses dense white routing below

BreakingTaps1 месяц назад
Agreed! Trying variations to lift / explode the active module more, and make the background less busy (darker colors, transparency, etc). Cheers!

FPGA Bandera1 месяц назад
Cant you use some kind of variation of map graphs?
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