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Playing around with ASIC render concepts. Need to work on visually differentiating the "active" module a bit more, but I think the bones are here.
56,281 просмотров • 2 месяцев назад •via X (Twitter)
Комментарии: 7

Matthew Venn2 месяцев назад
Have you seen ? For example this works great:

Ben Conrad2 месяцев назад
The grid. A digital frontier...

NanoPirate2 месяцев назад
Beautiful 🙌

LїckLїck🐈fellacat2 месяцев назад
that's pretty neat!

0xkato2 месяцев назад
In the X video, the active module reads clearly over green substrate, but loses separation in the angles where its pale interconnect texture crosses dense white routing below

BreakingTaps2 месяцев назад
Agreed! Trying variations to lift / explode the active module more, and make the background less busy (darker colors, transparency, etc). Cheers!

FPGA Bandera2 месяцев назад
Cant you use some kind of variation of map graphs?
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