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Playing around with ASIC render concepts. Need to work on visually differentiating the "active" module a bit more, but I think the bones are here.

56,281 次观看 • 2 个月前 •via X (Twitter)

7 条评论

Matthew Venn 的头像
Matthew Venn2 个月前

Have you seen ? For example this works great:

Ben Conrad 的头像
Ben Conrad2 个月前

The grid. A digital frontier...

NanoPirate 的头像
NanoPirate2 个月前

Beautiful 🙌

LїckLїck🐈fellacat 的头像
LїckLїck🐈fellacat2 个月前

that's pretty neat!

0xkato 的头像
0xkato2 个月前

In the X video, the active module reads clearly over green substrate, but loses separation in the angles where its pale interconnect texture crosses dense white routing below

BreakingTaps 的头像
BreakingTaps2 个月前

Agreed! Trying variations to lift / explode the active module more, and make the background less busy (darker colors, transparency, etc). Cheers!

FPGA Bandera 的头像
FPGA Bandera2 个月前

Cant you use some kind of variation of map graphs?

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