come warm yourself by my 100% FPGA logic 3D rasterization pipeline… while the geometry engine (also logic) cubes.
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3,488 triangle edition of the Utah teapot, environment mapped by a hardware geometry engine through my recreation of the SST-1 fixed function pipeline. Important note: because it is the Utah teapot, the bottom is missing. Wouldn't be right to add it. 100% FPGA hardware. Entirely SystemVerilog.
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I don’t have the BRAM for a depth buffer so it’s time to get the memory controller up and running for this fjord torus. 100% FPGA logic 3D pipeline, no CPU.
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a while ago Mikes Electric Stuff made a video about the different methods of driving LED displays w/FPGA covering PWM and gamma correction - very useful if you enjoy driving these yourself (I do).
