ML-assisted semi-automated chip reverse engineering workflow Now doing this kind of stuff takes a weekend and not months anymore

@furrtek mentioned earlier that template matching works quite well. I'm currently focused on fully automated wire tracing and verification processes.

@furrtek This though doesn't work on the image itself directly, it first uses an U-Net to find the vias, then it matches the cells on the via positions alone, which IMO works a lot better. But yeah, extracting the wires is still the biggest problem, how did you solve that?

Although I cannot reveal the details here, I need to create a dataset and train a wire tracing model in order to develop a tool that can be used with almost all gate arrays.

The challenging part is separating the three layers (poly+M0+M1) when they overlap on an unplanarized chip. I have an idea for an ML model that seems like it might work, but I haven't tried it yet because I need to create the dataset first.

Yeah exactly, I think that maybe recognizing the wires is easy, but it really gets challenging if you want to correctly solve overlapping stuff. When I do that by hand I always have to think where stuff might go and often it's literally about counting wires going in and out...

Wonderful!

there is a particular type of hardware emulation have been wanting to get going, this stuff is way beyond my level of understand...

What is this data?

Is it also possible to reverse-engineer built-in algorithms?

the merge step is most of the speedup. cell 34 alone is 38 instances

Super impressive stuff