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We cut open the Kirin 9030 and put it under an electron microscope. The smallest metal pitch measures 32.5 nanometers. That is tighter than Intel 18A, their brand new leading edge node. A Chinese fab with no EUV is out-pitching Intel's EUV node by roughly 10 percent. What's going... show more
1,017,918 Aufrufe • vor 2 Monaten •via X (Twitter)
37 Kommentare

AI-experts on X: THEY DISTILLED INTEL CODE COPY THEFT BAN COMMUNISM !!!!

Full breakdown here:

I’ve said so many times “do not underestimate China”

Semi companies built small features for years using multi-patterning. The issue is mask and processing costs (throughput) vs. EUV and CAD tool support. We built nm dimension devices to characterize at TI in the 1980's using tricks. There are many ways to skin a cat ;)

cc @CommunityNotes SemiAnalysis' teardown confirms the 32.5 nm M0 metal pitch on SMIC N+3 (Kirin 9030), tighter than Intel 18A's shipped 36 nm pitch. However, their full analysis notes this is a cherry-picked metric. Overall transistor density on N+3 (~113 MTr/mm²) trails Intel 18A by ~38% and is similar to TSMC N6. Intel's looser M0 pitch is a deliberate choice enabled by PowerVia backside power.

it's built on SMIC's 5nm class N+3 process using flat planar design. Kirin 2026 will use logical folding.

12nm, a ten year old tech has 32nm pitch. What’s up with that?

Are they really cut off from EUV?

Yes, SMIC uses DUV

Very interesting …. Hm hm hm

When a problem cannot be explained, there is another answer: China copied American technology.

Small metal pitch is relatively easy to do if you pair it with old generation transistor technology.

Before getting any wrong conclussions bassed on the headline alone, please watch the video. It's not that rosy.

They must have distilled it.

as most in foundry industry knows, you don’t necessarily need EUV to achieve smaller pitch. you just need the right process schemes to achieve this

两个月后华为会发布麒麟9050,那个才是正式采用他们最新的技术-韬定律的第一款芯片。

@highyieldYT This is a clickbait title. You guys are better than that.

Need semiconductor experience to answer this. EUV is not required for metal lines and is only used for transistor layers which is made of different layer/material. Also metal lines do not define technology node.

No EUV is fine

What's going on here? @grok did semianalysis provide the answer somewhere?

At the end of the day, this is still just pushing DUV multi-patterning to its absolute limit — not a real leap into the EUV era

So maybe they have EUV

18Aは1.8nmです 積層ピッチ32nmと言いますが敗戦幅と積層ピッチは関係ありません EUVで小さくなるのは配線幅であって積層ピッチではありません ナンセンス

Maybe China got their EUV machines via SGP or Thailand?

Well 18A can go down to 32nm in the future (maybe now) and if you're doing 32.5 with DUV tools that could take quad patterning (or more) with horrible yields

Maybe, maybe not. Even if they packed it as tight as you observed using whatever methodology, what's their yield?

But, but, Chinese can only copy, right? Right?!

可能是我过拟合了,但毫无疑问答案是他们蒸馏了Intel

Chinese have CUV

I don't believe this story that is portrayed that FABs are hard to build. I'm in a trade where it's hands on with electronics and machines. I don't see how making chips is that hard, yea it is hard but most of it is theory work, once the system is in place normal employees work in these FABs. It's just light burning channels in silicon then vapour despostion of metals in a chamber. Then acid etch and onto the next layer.

We gotta get you a lesson in pronouncing Chinese brand names. Huawei is a hard one but I know you've got this.

@lithos_graphein 👀!

Out pitching an EUV node without EUV is impressive engineering.

the question is what are the yields? you take the one that works well, but how many defects were made in order to make a working one?

a 32nm metal pitch doesn't mean anything

华为蒸馏了 EUV

It may be the yield issue. We don't how good the yield of Kirin. You can make very tight pitch, but if yield is very low, it doesn't make sense.
