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Forget GPUs. Map the RISC-V register file to HDMI, use it as a framebuffer, and blast RISC-V across the screen on a kianV bare-metal beast. Dave W Plummer

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logic destroyer

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57,837 görüntüleme • 1 yıl önce •via X (Twitter)

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Strap on our Troy Lee Designs enduro gloves and shred that donut with the gyro pure C on the KianV RISC-V HDMI SoC.
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Strap on our Troy Lee Designs enduro gloves and shred that donut with the gyro pure C on the KianV RISC-V HDMI SoC.

logic destroyer

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Allow me to introduce my RISC-V #KianV machine, which boots #Linux on the FPGA with SDRAM. It's a simple design, but powerful. Starting with my vacation. How awesome... Linux and RISC-V forever... #Verilog is my life. #riscv
2:07

Allow me to introduce my RISC-V #KianV machine, which boots #Linux on the FPGA with SDRAM. It's a simple design, but powerful. Starting with my vacation. How awesome... Linux and RISC-V forever... #Verilog is my life. #riscv

Logic Destroyer — Proven in Silicon.

101,726 görüntüleme • 3 yıl önce

I can't believe I dared to do it: an iCE40HX8K FPGA that boots a mainline 6.13.0-rc1 #Linux kernel via OpenSBI, running 100% KianV SV32 (MMU) RV32IMA Zicntr Zicsr Zifencei SSTC RISC-V. Incredible... amazing board, thanks to Machdyne UG's Kuchen iCE40HX8K FPGA board. #ice40 RISC-V International YosysHQ
12:00

I can't believe I dared to do it: an iCE40HX8K FPGA that boots a mainline 6.13.0-rc1 #Linux kernel via OpenSBI, running 100% KianV SV32 (MMU) RV32IMA Zicntr Zicsr Zifencei SSTC RISC-V. Incredible... amazing board, thanks to Machdyne UG's Kuchen iCE40HX8K FPGA board. #ice40 RISC-V International YosysHQ

Logic Destroyer — Proven in Silicon.

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It is a significant milestone that today we are able to demonstrate our capabilities in terms of high-performance chip design in the RISC-V domain. Addressed the national roadshow on Digital India RISC-V Vega Processors and shared that PM Narendra Modi ji’s govt is all in and completely backs the RISC-V architecture in terms of developing chips, devices, etc for the Indian ecosystem and for the world. This roadshow showcases our ambitions to become one of the world’s leading nations in creating innovation around the RISC-V ISA and the DIR-V family of chips and systems. The program will be fueled by the creativity and innovation of our engineers and startups. #RISV #DiRV #NewIndia #IndiaTechade
11:33

It is a significant milestone that today we are able to demonstrate our capabilities in terms of high-performance chip design in the RISC-V domain. Addressed the national roadshow on Digital India RISC-V Vega Processors and shared that PM Narendra Modi ji’s govt is all in and completely backs the RISC-V architecture in terms of developing chips, devices, etc for the Indian ecosystem and for the world. This roadshow showcases our ambitions to become one of the world’s leading nations in creating innovation around the RISC-V ISA and the DIR-V family of chips and systems. The program will be fueled by the creativity and innovation of our engineers and startups. #RISV #DiRV #NewIndia #IndiaTechade

Rajeev Chandrasekhar 🇮🇳

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Back in May 2022, when I got my first program running on a bare-metal RISC-V SoC that fits into an iCE40HX1K FPGA with only 1280 LUTs... that was some crazy shit!
0:25

Back in May 2022, when I got my first program running on a bare-metal RISC-V SoC that fits into an iCE40HX1K FPGA with only 1280 LUTs... that was some crazy shit!

logic destroyer

20,086 görüntüleme • 1 yıl önce

Wrote a brutal C++23 CPU monitor for my KianV RISC-V Linux SoC on FPGA. It uses 8 GPIO LEDs to show live CPU load. Clean modern C++, signal-safe shutdown, no mercy , just pure hardware feedback.
2:33

Wrote a brutal C++23 CPU monitor for my KianV RISC-V Linux SoC on FPGA. It uses 8 GPIO LEDs to show live CPU load. Clean modern C++, signal-safe shutdown, no mercy , just pure hardware feedback.

Logic Destroyer — Proven in Silicon.

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Let's write C++23 code in an academic style. I aim to implement a modern C++ threading example using 100 threads—both with and without mutex protection—on my self-designed, from-scratch RISC-V Linux SoC, KianV
2:17

Let's write C++23 code in an academic style. I aim to implement a modern C++ threading example using 100 threads—both with and without mutex protection—on my self-designed, from-scratch RISC-V Linux SoC, KianV

Logic Destroyer — Proven in Silicon.

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At #UbuntuSummit 2024, Nirav Patel, CEO of Framework, wowed the audience by swapping the Mainboard on a Framework Laptop to convert it from an x86 processor to a RISC-V processor, both of which support Ubuntu.
4:46

At #UbuntuSummit 2024, Nirav Patel, CEO of Framework, wowed the audience by swapping the Mainboard on a Framework Laptop to convert it from an x86 processor to a RISC-V processor, both of which support Ubuntu.

Ubuntu

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🤓🤖🚀 Robojam: To Celebrate Robonomics Launch on Polkadot! Instead of the traditional red ribbon, we decided to showcase the longest open-source chain of 2024, built on a RISC-V architecture. Watch the video and learn more:
2:10

🤓🤖🚀 Robojam: To Celebrate Robonomics Launch on Polkadot! Instead of the traditional red ribbon, we decided to showcase the longest open-source chain of 2024, built on a RISC-V architecture. Watch the video and learn more:

Airalab 🛠 Robonomics

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Linea Insights📺 Season 1, Episode 2. "From direct EVM arithmetization to a RISC-V based zkVM. What does this mean and why has the team made this decision?"
1:40

Linea Insights📺 Season 1, Episode 2. "From direct EVM arithmetization to a RISC-V based zkVM. What does this mean and why has the team made this decision?"

Linea.eth

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Yo, testing KianV StealthV on the Genesis 2 now with 1 GB of RAM and 100 MHz. This feels fucking awesome. DDR RAM is pure porn. Custom RISC-V Linux running on my own five-stage pipeline CPU. What more could you want? Of course, a badass out-of-order core is coming later. It's still in the design phase, though.
5:33

Yo, testing KianV StealthV on the Genesis 2 now with 1 GB of RAM and 100 MHz. This feels fucking awesome. DDR RAM is pure porn. Custom RISC-V Linux running on my own five-stage pipeline CPU. What more could you want? Of course, a badass out-of-order core is coming later. It's still in the design phase, though.

Logic Destroyer — Proven in Silicon.

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Introducing "Linea Insights" 📺 A series where Linea's cryptography team shares what we are building and the thinking behind it. Following our announcement at Ethproofs, Olivier Bégassat walks us through the shift from direct EVM arithmetization to RISC-V.
1:05

Introducing "Linea Insights" 📺 A series where Linea's cryptography team shares what we are building and the thinking behind it. Following our announcement at Ethproofs, Olivier Bégassat walks us through the shift from direct EVM arithmetization to RISC-V.

Linea.eth

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“A cutting edge blueprint for the future of semiconductor chip design, called ‘RISC-V’… got it’s start right here on the campus of UC Berkeley. The same Berkeley professor who helped create the technology, is now partnering with Tsinghua University in China… The problem is that the TBSI partnership has a record of collaboration with Chinese military-linked universities. We must make sure that advanced technologies, such as RISC-V, developed through federal funding support are not being transferred to China by way of under-regulated collaborations between U.S. and Chinese universities at the cost of America’s national security.” - Chairman
1:09

“A cutting edge blueprint for the future of semiconductor chip design, called ‘RISC-V’… got it’s start right here on the campus of UC Berkeley. The same Berkeley professor who helped create the technology, is now partnering with Tsinghua University in China… The problem is that the TBSI partnership has a record of collaboration with Chinese military-linked universities. We must make sure that advanced technologies, such as RISC-V, developed through federal funding support are not being transferred to China by way of under-regulated collaborations between U.S. and Chinese universities at the cost of America’s national security.” - Chairman

Select Committee on China

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fixes a gap in crypto privacy. Traditional privacy coins like Monero and Zcash protect transactions, but not computation. App logic, user data, and state transitions are still exposed. Our RISC V privacy runtime brings deterministic execution, zkSNARK proofs, and fast cryptographic precompiles into one framework, letting anyone build private AI, private DeFi, private data collaboration, and private bridges/apps. Privacy moves from value to computation. Now available on the open-source privacy platform (OSPP). Enjoy this fun demo we built. Feel free to replicate the steps and try our RISC V privacy runtime yourself~!
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fixes a gap in crypto privacy. Traditional privacy coins like Monero and Zcash protect transactions, but not computation. App logic, user data, and state transitions are still exposed. Our RISC V privacy runtime brings deterministic execution, zkSNARK proofs, and fast cryptographic precompiles into one framework, letting anyone build private AI, private DeFi, private data collaboration, and private bridges/apps. Privacy moves from value to computation. Now available on the open-source privacy platform (OSPP). Enjoy this fun demo we built. Feel free to replicate the steps and try our RISC V privacy runtime yourself~!

Monero-Chan

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Linea Insights 📺 Season 1, Episode 12. Today, we conclude Season 1 of Linea Insights with one final question for Olivier Bégassat: "What makes you personally excited about the move to RISC-V?" Across these twelve episodes, we had the opportunity to hear the full perspective of our Arithmetization Lead following the announcement of our move from a zkEVM to a RISC-V zkVM back in March. We answered a wide range of questions: → What are the impacts of this change in terms of simplification, compatibility, security, and more? → Why did we decide to make this change now? → What will differentiate us from the many teams currently building a RISC-V zkVM? → What performance can we expect? It has been a real pleasure to share Olivier’s exceptional knowledge with you throughout the season. We hope these episodes gave you a better understanding of some of the complex topics our arithmetization team is currently working on. Our next season will focus on gnark, our open-source zero-knowledge library written in Go and used by several projects across the ecosystem. Together with Youssef | yelhousni.eth, we will explore gnark from every angle. More coming soon! Below is a thread with all the videos from this season, to watch or rewatch! 💙
2:24

Linea Insights 📺 Season 1, Episode 12. Today, we conclude Season 1 of Linea Insights with one final question for Olivier Bégassat: "What makes you personally excited about the move to RISC-V?" Across these twelve episodes, we had the opportunity to hear the full perspective of our Arithmetization Lead following the announcement of our move from a zkEVM to a RISC-V zkVM back in March. We answered a wide range of questions: → What are the impacts of this change in terms of simplification, compatibility, security, and more? → Why did we decide to make this change now? → What will differentiate us from the many teams currently building a RISC-V zkVM? → What performance can we expect? It has been a real pleasure to share Olivier’s exceptional knowledge with you throughout the season. We hope these episodes gave you a better understanding of some of the complex topics our arithmetization team is currently working on. Our next season will focus on gnark, our open-source zero-knowledge library written in Go and used by several projects across the ecosystem. Together with Youssef | yelhousni.eth, we will explore gnark from every angle. More coming soon! Below is a thread with all the videos from this season, to watch or rewatch! 💙

Linea.eth

36,359 görüntüleme • 2 ay önce

Getting started with Hardware Design is as easy as 1, 2, 3, 4... 1. Draw the circuit using building blocks. 2. Map the inputs and output to FPGA pins. 3. Verify and Build. 4. Upload to the board! And you can do pretty serious stuff with this. While we start with iCEStudio (visual blocks based design) we don't have to stick to that. We can just as well write hardware using HDL and fire the compiler etc ourselves. The LUT count on the FPGA is enough to deploy a tiny RISC-V based SoC! Yes! From the Basics of Digital Electronics to customizing a RISC-V based SoC - Soan Papdi is your companion on the journey! Lectures on the basics will be uploaded to YouTube. Lectures on CPU/SoC related topics will be made available to the Library Subscribers. + You can learn more about Soan Papdi FPGA here: + You can join the Library Access with a 70% Discount here: IMPORTANT: We will revise the prices of Library Access, effective 9th Feb.
0:23

Getting started with Hardware Design is as easy as 1, 2, 3, 4... 1. Draw the circuit using building blocks. 2. Map the inputs and output to FPGA pins. 3. Verify and Build. 4. Upload to the board! And you can do pretty serious stuff with this. While we start with iCEStudio (visual blocks based design) we don't have to stick to that. We can just as well write hardware using HDL and fire the compiler etc ourselves. The LUT count on the FPGA is enough to deploy a tiny RISC-V based SoC! Yes! From the Basics of Digital Electronics to customizing a RISC-V based SoC - Soan Papdi is your companion on the journey! Lectures on the basics will be uploaded to YouTube. Lectures on CPU/SoC related topics will be made available to the Library Subscribers. + You can learn more about Soan Papdi FPGA here: + You can join the Library Access with a 70% Discount here: IMPORTANT: We will revise the prices of Library Access, effective 9th Feb.

Piyush Itankar

13,148 görüntüleme • 6 ay önce