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Forget GPUs. Map the RISC-V register file to HDMI, use it as a framebuffer, and blast RISC-V across the screen on a kianV bare-metal beast. Dave W Plummer

logic destroyer

20,848 subscribers

57,837 次观看 • 1 年前 •via X (Twitter)

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Strap on our Troy Lee Designs enduro gloves and shred that donut with the gyro pure C on the KianV RISC-V HDMI SoC.

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logic destroyer

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Allow me to introduce my RISC-V #KianV machine, which boots #Linux on the FPGA with SDRAM. It's a simple design, but powerful. Starting with my vacation. How awesome... Linux and RISC-V forever... #Verilog is my life. #riscv

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I can't believe I dared to do it: an iCE40HX8K FPGA that boots a mainline 6.13.0-rc1 #Linux kernel via OpenSBI, running 100% KianV SV32 (MMU) RV32IMA Zicntr Zicsr Zifencei SSTC RISC-V. Incredible... amazing board, thanks to Machdyne UG's Kuchen iCE40HX8K FPGA board. #ice40 RISC-V International YosysHQ

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It is a significant milestone that today we are able to demonstrate our capabilities in terms of high-performance chip design in the RISC-V domain. Addressed the national roadshow on Digital India RISC-V Vega Processors and shared that PM Narendra Modi ji’s govt is all in and completely backs the RISC-V architecture in terms of developing chips, devices, etc for the Indian ecosystem and for the world. This roadshow showcases our ambitions to become one of the world’s leading nations in creating innovation around the RISC-V ISA and the DIR-V family of chips and systems. The program will be fueled by the creativity and innovation of our engineers and startups. #RISV #DiRV #NewIndia #IndiaTechade

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Back in May 2022, when I got my first program running on a bare-metal RISC-V SoC that fits into an iCE40HX1K FPGA with only 1280 LUTs... that was some crazy shit!

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“A cutting edge blueprint for the future of semiconductor chip design, called ‘RISC-V’… got it’s start right here on the campus of UC Berkeley. The same Berkeley professor who helped create the technology, is now partnering with Tsinghua University in China… The problem is that the TBSI partnership has a record of collaboration with Chinese military-linked universities. We must make sure that advanced technologies, such as RISC-V, developed through federal funding support are not being transferred to China by way of under-regulated collaborations between U.S. and Chinese universities at the cost of America’s national security.” - Chairman

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fixes a gap in crypto privacy. Traditional privacy coins like Monero and Zcash protect transactions, but not computation. App logic, user data, and state transitions are still exposed. Our RISC V privacy runtime brings deterministic execution, zkSNARK proofs, and fast cryptographic precompiles into one framework, letting anyone build private AI, private DeFi, private data collaboration, and private bridges/apps. Privacy moves from value to computation. Now available on the open-source privacy platform (OSPP). Enjoy this fun demo we built. Feel free to replicate the steps and try our RISC V privacy runtime yourself~!

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Getting started with Hardware Design is as easy as 1, 2, 3, 4... 1. Draw the circuit using building blocks. 2. Map the inputs and output to FPGA pins. 3. Verify and Build. 4. Upload to the board! And you can do pretty serious stuff with this. While we start with iCEStudio (visual blocks based design) we don't have to stick to that. We can just as well write hardware using HDL and fire the compiler etc ourselves. The LUT count on the FPGA is enough to deploy a tiny RISC-V based SoC! Yes! From the Basics of Digital Electronics to customizing a RISC-V based SoC - Soan Papdi is your companion on the journey! Lectures on the basics will be uploaded to YouTube. Lectures on CPU/SoC related topics will be made available to the Library Subscribers. + You can learn more about Soan Papdi FPGA here: + You can join the Library Access with a 70% Discount here: IMPORTANT: We will revise the prices of Library Access, effective 9th Feb.

Getting started with Hardware Design is as easy as 1, 2, 3, 4... 1. Draw the circuit using building blocks. 2. Map the inputs and output to FPGA pins. 3. Verify and Build. 4. Upload to the board! And you can do pretty serious stuff with this. While we start with iCEStudio (visual blocks based design) we don't have to stick to that. We can just as well write hardware using HDL and fire the compiler etc ourselves. The LUT count on the FPGA is enough to deploy a tiny RISC-V based SoC! Yes! From the Basics of Digital Electronics to customizing a RISC-V based SoC - Soan Papdi is your companion on the journey! Lectures on the basics will be uploaded to YouTube. Lectures on CPU/SoC related topics will be made available to the Library Subscribers. + You can learn more about Soan Papdi FPGA here: + You can join the Library Access with a 70% Discount here: IMPORTANT: We will revise the prices of Library Access, effective 9th Feb.

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13,148 次观看 • 8 个月前