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My 286-class CPU (real-mode only) is finally working in sim and we have PC-AT BIOS, VGA and IBM Basic working.😀 The CPU is written from scratch and uses a 5-stage pipeline, aiming to be fast enough to run early 90's games. The final core will be in between ao486... show more
16,344 次观看 • 1 年前 •via X (Twitter)
13 条评论

Is this for Tang Console?

Yes. And it should straightforward to port to other FPGAs.

Try it. You'll never look back.

do you use microcode?

Most instructions are hardwired. Complex instructions like string ones are microcoded. So in good conditions, the pipeline could finish one instruction per cycle. Overally I try to follow the 80486 design.

What is the operating frequency ?

The main goal is lower cycles-per-instruction. It'll be a win if we can achieve 2 to 3 CPI, with 40-80Mhz Fmax. Current x86 softcores all have pretty poor CPI.

can we have same in risc-v also is there any book about concepts and step by step guide about this?

VexRiscv is a popular riscv softcore. For getting your hands dirty, you need a FPGA retro-gaming / retro-computing distribution. You can try MiSTer or my TangCore.

A Raspberry Pi CM5 laptop. Would you like to know more?

Very excited about this one, fresh from wafer dicing 🔍 I received the custom silicon-based inductors from Würth Elektronik that will be embedded in the SiP for the open-source smartwatch 🙌

Ladies and gentlemen! The first design for the #Gowin GW5A chip series to fully pass the whole Yosys->Nextpnr->Apicula->working-board chain!🍾 🍾 🍾 The design itself is nothing to write home about - just an inversion of the LED button, #fpga #sipeed #gowin #apicula

what circuit board..
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Oliver
57,669 次观看 • 2 年前
