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Logic Destroyer — Proven in Silicon.

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I breed Linux ASICs.

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MP3 playback on a custom Linux RISC-V FPGA SoC. What more could you want?

MP3 playback on a custom Linux RISC-V FPGA SoC. What more could you want?

Logic Destroyer — Proven in Silicon.

22,133 次观看 • 9 天前

Ok bro... we have a 32-bit counter. Let it count 1 tick per second and wait 136 years, 70 days, 6 hours, 28 minutes, and 16 seconds for rollover, or just count 1,000,000 ticks per second and wait only 1 hour, 11 minutes, and 35 seconds.

Ok bro... we have a 32-bit counter. Let it count 1 tick per second and wait 136 years, 70 days, 6 hours, 28 minutes, and 16 seconds for rollover, or just count 1,000,000 ticks per second and wait only 1 hour, 11 minutes, and 35 seconds.

logic destroyer

40,199 次观看 • 1 个月前

Yo, testing KianV StealthV on the Genesis 2 now with 1 GB of RAM and 100 MHz. This feels fucking awesome. DDR RAM is pure porn. Custom RISC-V Linux running on my own five-stage pipeline CPU. What more could you want? Of course, a badass out-of-order core is coming later. It's still in the design phase, though.

Yo, testing KianV StealthV on the Genesis 2 now with 1 GB of RAM and 100 MHz. This feels fucking awesome. DDR RAM is pure porn. Custom RISC-V Linux running on my own five-stage pipeline CPU. What more could you want? Of course, a badass out-of-order core is coming later. It's still in the design phase, though.

Logic Destroyer — Proven in Silicon.

21,848 次观看 • 1 个月前

KianV Stealth Linux RISC-V SoC. First bring-up with a 5-stage pipeline CPU and GShare branch prediction. Running at 25 MHz for now during bring-up, but already timing clean at 50 MHz. Ported my old SoC parts like SDRAM controller and UART to the new pipeline core. Caches are still primitive, memory is single-beat and one clock domain only. Tons of potential left. Fun summer ahead.

KianV Stealth Linux RISC-V SoC. First bring-up with a 5-stage pipeline CPU and GShare branch prediction. Running at 25 MHz for now during bring-up, but already timing clean at 50 MHz. Ported my old SoC parts like SDRAM controller and UART to the new pipeline core. Caches are still primitive, memory is single-beat and one clock domain only. Tons of potential left. Fun summer ahead.

logic destroyer

39,786 次观看 • 2 个月前

Celebrating KianV RISC-V Chip Design

Celebrating KianV RISC-V Chip Design

Logic Destroyer — Proven in Silicon.

74,167 次观看 • 8 个月前

A small step for a hobby logic designer, but a giant leap for Tiny Tapeout. The first official RISC-V uLinux ASIC, yes, ASIC, you heard that right, is operational and functional. Just dabbling in chip design as a hobbyist. Haha, what an awesome achievement! Thanx to Matthew Venn Uri Shaked tnt's public account Rebellmike troyburn psychogenic #tinytapeout #chipdesign #verilog #130nm #Skywater #yosys #openlane Wokwi #logicDesign #logicDestroyer

A small step for a hobby logic designer, but a giant leap for Tiny Tapeout. The first official RISC-V uLinux ASIC, yes, ASIC, you heard that right, is operational and functional. Just dabbling in chip design as a hobbyist. Haha, what an awesome achievement! Thanx to Matthew Venn Uri Shaked tnt's public account Rebellmike troyburn psychogenic #tinytapeout #chipdesign #verilog #130nm #Skywater #yosys #openlane Wokwi #logicDesign #logicDestroyer

logic destroyer

147,395 次观看 • 2 年前

Dude, I haven’t touched my CPU since February. Getting back into it is crazy, but I just brought it back to life—synthesized and simulated. Can’t wait to hack on it again at the end of the month. It’s insanely fast and will be a Linux CPU. I’m super hyped. SystemVerilog forever.

Dude, I haven’t touched my CPU since February. Getting back into it is crazy, but I just brought it back to life—synthesized and simulated. Can’t wait to hack on it again at the end of the month. It’s insanely fast and will be a Linux CPU. I’m super hyped. SystemVerilog forever.

logic destroyer

50,026 次观看 • 7 个月前

Forget GPUs. Map the RISC-V register file to HDMI, use it as a framebuffer, and blast RISC-V across the screen on a kianV bare-metal beast. Dave W Plummer

Forget GPUs. Map the RISC-V register file to HDMI, use it as a framebuffer, and blast RISC-V across the screen on a kianV bare-metal beast. Dave W Plummer

logic destroyer

57,837 次观看 • 11 个月前

Allow me to introduce my RISC-V #KianV machine, which boots #Linux on the FPGA with SDRAM. It's a simple design, but powerful. Starting with my vacation. How awesome... Linux and RISC-V forever... #Verilog is my life. #riscv

Allow me to introduce my RISC-V #KianV machine, which boots #Linux on the FPGA with SDRAM. It's a simple design, but powerful. Starting with my vacation. How awesome... Linux and RISC-V forever... #Verilog is my life. #riscv

logic destroyer

101,688 次观看 • 3 年前

May 2022: Kianv RISC-V Baremetal Achievement

May 2022: Kianv RISC-V Baremetal Achievement

logic destroyer

50,767 次观看 • 1 年前

Let's write C++23 code in an academic style. I aim to implement a modern C++ threading example using 100 threads—both with and without mutex protection—on my self-designed, from-scratch RISC-V Linux SoC, KianV

Let's write C++23 code in an academic style. I aim to implement a modern C++ threading example using 100 threads—both with and without mutex protection—on my self-designed, from-scratch RISC-V Linux SoC, KianV

logic destroyer

42,714 次观看 • 1 年前

Only UART. No VGA, no framebuffer. Just UART. Picked up my pipelined CPU Kian StealthV again after not touching it for a year. Just playing around a bit to get back into it and find the motivation to push it towards a Linux SoC.

Only UART. No VGA, no framebuffer. Just UART. Picked up my pipelined CPU Kian StealthV again after not touching it for a year. Just playing around a bit to get back into it and find the motivation to push it towards a Linux SoC.

logic destroyer

16,861 次观看 • 4 个月前

My 9-year-old son's design works! I'm giving it to him to take to school so he can tell everyone he's a hobby chip designer.

My 9-year-old son's design works! I'm giving it to him to take to school so he can tell everyone he's a hobby chip designer.

logic destroyer

25,773 次观看 • 1 年前

Back in May 2022, when I got my first program running on a bare-metal RISC-V SoC that fits into an iCE40HX1K FPGA with only 1280 LUTs... that was some crazy shit!

Back in May 2022, when I got my first program running on a bare-metal RISC-V SoC that fits into an iCE40HX1K FPGA with only 1280 LUTs... that was some crazy shit!

logic destroyer

20,086 次观看 • 1 年前

Logic Destroyer. ULX3S in hand. Oakleys on. Texture Gouraud Shading running on his own KianV RISC V SoC. Witness this is what Logic Destroyer looks like.

Logic Destroyer. ULX3S in hand. Oakleys on. Texture Gouraud Shading running on his own KianV RISC V SoC. Witness this is what Logic Destroyer looks like.

logic destroyer

15,961 次观看 • 11 个月前

Wrote a brutal C++23 CPU monitor for my KianV RISC-V Linux SoC on FPGA. It uses 8 GPIO LEDs to show live CPU load. Clean modern C++, signal-safe shutdown, no mercy , just pure hardware feedback.

Wrote a brutal C++23 CPU monitor for my KianV RISC-V Linux SoC on FPGA. It uses 8 GPIO LEDs to show live CPU load. Clean modern C++, signal-safe shutdown, no mercy , just pure hardware feedback.

logic destroyer

17,844 次观看 • 1 年前

HDMI donut by Logic Destroyer and his KianV bare-metal SoC.

HDMI donut by Logic Destroyer and his KianV bare-metal SoC.

Silicon Proven Destroyer

15,447 次观看 • 11 个月前

Strap on our Troy Lee Designs enduro gloves and shred that donut with the gyro pure C on the KianV RISC-V HDMI SoC.

Strap on our Troy Lee Designs enduro gloves and shred that donut with the gyro pure C on the KianV RISC-V HDMI SoC.

logic destroyer

14,218 次观看 • 11 个月前

It’s still crazy that an iCE40HX8K FPGA runs the Linux 6.15-rc1 mainline kernel with networking. It’s crazy. KianV RISC-V has lost its innocence.

It’s still crazy that an iCE40HX8K FPGA runs the Linux 6.15-rc1 mainline kernel with networking. It’s crazy. KianV RISC-V has lost its innocence.

logic destroyer

17,416 次观看 • 1 年前